1. Field of the Invention
The present invention relates to a method for manufacturing a thin film transistor (TFT) substrate which is used in a liquid crystal display apparatus or a display apparatus using an organic electroluminescence device. More particularly, the present invention relates to a method for manufacturing a CMOS TFT substrate on which an n-type thin film transistor (TFT) and a p-type thin film transistor are included.
2. Description of the Related Art
A thin film transistor (hereinafter, referred to as TFT in some cases) is used in a liquid crystal display apparatus or the like. In a case where drive circuits are formed on a substrate in addition to pixels, there is generally used a TFT including a polycrystalline Si film, which is capable of providing high mobility. Particularly, a so-called CMOS TFT substrate on which both of n-type TFTs and p-type TFTs are formed has an advantage of flexibility in circuit design, compared with a TFT substrate on which only n-type TFTs are formed. However, there has conventionally been a problem that the number of masks used in manufacturing is increased.
In general, one more mask is required for formation of sources and drains of the p-type TFTs. In a case where threshold values are individually adjusted for the p-type TFTs and the n-type TFTs, another mask is required. As a method for reducing the number of masks, a contact process with pixel electrodes is eliminated. Further, a mask having semitransparent regions besides transparent regions and opaque regions, that is, a half-tone mask, is used to reduce the number of masks.
Examples of a method for unifying processing of a semiconductor film and processing of a metal film by using the half-tone mask, and a method for eliminating contacts with pixel electrodes are disclosed, for example, in SID 07 DIGEST, p. 73 (2007). An example of a method for unifying masks which are used for doping at a time of forming a gate and a source and drain is disclosed, for example, in JP 2002-217429 A and JP 2007-72451 A.
An example of a method for manufacturing a gate and doping for a semiconductor film of a CMOS TFT substrate according to a conventional technology, in which the half-tone mask is used, is shown in FIG. 19. FIG. 19 is a view showing mask patterns used in the manufacturing method and the structure of the TFT substrate obtained by using the mask patterns. Impurity implantation into an n-type TFT, a p-type TFT, and a capacitor, and electrode formation are performed by using three masks including two masks MSK1, MSK2 and a half-tone mask HMK. Note that FIG. 20 is a table showing correspondence relations between the mask patterns and respective regions of members formed on the TFT substrate. Each end of a channel PCH of the p-type TFT is defined by a boundary between an opaque region BL of the half-tone mask HMK and a transparent region OP thereof. Further, each end of a channel NCH of the n-type TFT is defined by a boundary between the opaque region BL of the half-tone mask HMK and a semitransparent region HT thereof, and a boundary between the opaque region BL of the half-tone mask HMK and the transparent region OP thereof, respectively.
Further, FIGS. 21A to 21D and 22A to 22D are process views showing an example of a method for manufacturing the TFT substrate shown in FIG. 19. In FIG. 21A, polysilicon PSI films are patterned on a glass substrate GLS via an undercoat film UDC, and a gate insulating film GI and metal films M1 and M2 are laminated thereon. Then, a thick-film resist pattern RST which corresponds to the opaque region BL and a thin-film resist pattern TFR which corresponds to the semitransparent region HT are formed by using the half-tone mask HMK. The metal films M2 and M1 are simultaneously etched to obtain a shape shown in FIG. 21C, and then the thin-film resist is removed by ashing. In this case, part of the thick-film resist is also removed and a dimension thereof is reduced. The metal film M2 is etched by using the remaining resist as a mask. After that, n-type impurities are implanted at low concentration via the metal film M1 and the gate insulating film GI, and gate overlapped drains GLD are formed, thereby obtaining the structure shown in FIG. 21D. After the resist is removed, the n-type impurities are implanted over the entire surface at high concentration and at low acceleration, and a source and drain NSD of the n-type TFT is formed by using the metal films M1 and M2 as masks. In addition, a different mask is used to form the resist pattern RST, and the n-type impurities are implanted to form a lower capacitor electrode BD, while protecting the TFTs, thereby obtaining the structure shown in FIG. 22B. After the resist is removed, as shown in FIG. 22C, a different mask is used to form the resist pattern RST for covering the n-type TFT and the capacitor, and p-type impurities are implanted at higher concentration than that of the n-type impurities to form a source and drain PSD of the p-type TFT. Then, the resist is removed, thereby obtaining the structure shown in FIG. 22D. With the three masks, the gates, the sources, and the drains of the n-type TFT and the p-type TFT, and the lower capacitor electrode are formed.
However, in the case where the processing of the semiconductor film and the processing of the metal film are unified by using the half-tone mask, the above-mentioned method for manufacturing the TFT substrate involves a problem of increasing the manufacturing processes in which another insulating film is provided so as to prevent metal contamination in the channels made of the semiconductor films.
Further, in the case of eliminating the contacts with the pixel electrodes, a layout of the pixel electrodes is limited and there arises a problem that an aperture ratio is reduced. A method for unifying only a gate formation and doping has an advantage in that the number of masks can be reduced without changing the layout around the pixel electrodes, which has influence on the aperture ratio. However, conventionally, the method has not sufficed to stably form a channel length which affects TFT characteristics. Specifically, the use of a pattern which defines the boundaries of the sources, the drains, and the channels by using the boundaries of the opaque region of the half-tone mask, and variation in amount of regression at a time of resist ashing have caused a problem of inconstant channel length. For example, in the above-mentioned structural example shown in FIG. 19, the second metal film M2 for a gate PGT of the p-type TFT and the second metal film M2 for a gate NGT of the n-type TFT are formed by a pattern obtained by ashing of the resist pattern corresponding to the opaque region of the half-tone mask in the manufacturing process shown in FIG. 21D, and the second metal films M2 are affected by the amount of regression due to ashing of the resist pattern RST. Accordingly, dimension accuracy is degraded. Because the second metal film for the gate PGT corresponds to the channel PCH of the p-type TFT as shown in FIG. 22C, and the second metal film for the gate NGT corresponds to the channel NCH of the n-type TFT as shown in FIG. 21D, the dimension accuracy of the channel length is degraded.
Further, conventional methods have involved a problem that, in order to individually adjust the threshold values of the n-type TFT and the p-type TFT, another mask is required to adjust impurity concentrations for the channels even when the half-tone mask is used.